Synopsys has donated a library of advanced SystemVerilog assertion checkers defined in the ARM-Synopsys Verification Methodology Manual (VMM) for SystemVerilog to Accellera, the electronic design automation (EDA) organization focused on EDA standards. Provided as SystemVerilog source code, the check...

VeriEZ Solutions announced two pre-packaged sets of guidelines (“rulesets”) for design and verification teams. The rulesets complement existing rulesets in EZVerify, VeriEZ’s productivity solution for OpenVera and SystemVerilog-based design and verification teams. EZVerify utilizes static analysis t...

JTAG Technologies` boundary-scan tools support the advanced security features of Altera`s Stratix II FPGA family. The security solution offered in Stratix II FPGAs uses an advanced encryption standard (AES) along with a 128-bit non-volatile key, and is usefull for applications requiring design flexi...

Denali announced availability of its design core for PCIe technology. The PCIe core provides hardware developers with a silicon-proven solution for deploying PCI Express technology. The product is part of Denali’s Databahn line of IP, which also includes configurable memory controller IP for DDR and...

Actel announced prototype availability of the RTAX4000S, a four million-gate FPGA. The RTAX4000S is suited for satellite payload systems that require high gate counts, such as data processing applications in communications, earth observation and scientific satellites. Like the flight units of the ra...