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PLD/FPGA/ASIC/EDA ARCHIV

30. 03. 06 User configurable IP cores for Lattice devices

Lattice Semiconductor announced the availability of several ispLeverCORE Intellectual Property (IP) modules that are user configurable via its IPexpress design flow. The IPexpress flow is included as a standard feature in Lattice’s ispLEVER design tool suite and supported functions include DDR, Ethe...

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20. 03. 06 Simucad-Spice Models: LDMOS and HV MOS

Simucad Design Automation announced today availability of LDMOS and HV MOS Compact Spice Models for its SmartSpice analog simulator and SmartSpiceRF Harmonic-based simulator. LDMOS is based on the Philips' LDMOS compact model and HV MOS compact model is based on the popular BSIM3 from the University...

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17. 03. 06 Flomerics interface to Cadence Allegro PCB Editor

Flomerics has introduced Version 3.0 of its FLO/PCB thermal design software, FLO/PCB for Allegro, which provides a link to Cadence Allegro PCB Editor software. Designers can call up a menu item on the Cadence software and generate a thermal model of their design. They can analyze the design from a t...

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06. 03. 06 ARM releases AMBA 3 AXI Assertions

ARM announced the production release of AMBA 3 AXI assertions to enable accelerated design and verification of AMBA 3 AXI fabric-based SoCs. Any company can obtain the assertions from ARM in source format, without paying royalties or license fees. The assertions provide a definitive description of t...

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