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PLD/FPGA/ASIC/EDA ARCHIV

31. 10. 06 In-system programmable, single-ended clock buffer

Lattice Semiconductor has expanded its ispClock 5300S family of in-system programmable, single-ended clock buffer devices with the release of the pin-compatible ispClock5316S (16-output) and the ispClock5320S (20-output) ICs. The E2CMOS-based ispClock5300S device family now offers programmable clock...

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18. 10. 06 FPGAs with built-in PCI Express block

Xilinx announced initial shipments of its Virtex-5 LXT field programmable gate arrays (FPGAs). The second of four domain-optimized platforms in the new Virtex-5 family, the LXT platform series is the first FPGA to deliver a hard-coded PCI Express Endpoint and Tri-mode Ethernet Media Access Controlle...

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13. 10. 06 Debug Package for Xilinx FPGAs

Tektronix and First Silicon Solutions (FS2) announced the FPGAView software package for Tektronix TLA Series logic analyzers that enables real-time debugging of Xilinx FPGAs. Using the FPGAView software, design engineers can measure signals inside their Xilinx FPGA design and select which group of i...

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09. 10. 06 Automotive Grade AEC-Q100 certified CPLDs

Lattice Semiconductor announced that automotive versions of its ispMACH 4000Z CPLDs (Complex Programmable Logic Devices) have been characterized and qualified to meet the certification requirements of the AEC-Q100 standard as defined by the Automotive Electronics Council (AEC). Production quantities...

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02. 10. 06 Library with ARM PrimeCell Models and AXI Bus

VaST Systems Technology announced the availability of VaST models of the ARM PrimeCell PL080 DMA Controller, PL011 UART, PL190 Vector Interrupt Controller, PL131 Smart Card Interface, and the AMBA AXI bus. The company provide a system engineering environment for the design of embedded systems and sy...

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