Silicon Logic Engineering, a semiconductor design services division of Tundra Semiconductor, announced the development of a licensable Interlaken protocol IP core for use in ASIC or FPGA designs. The Interlaken IP Core is scalable, with early versions providing from 10Gbps to 60+Gbps bandwidth acros...

Lattice will offer its customers a special edition of Aldec’s Active-HDL Designer Edition tools for FPGA design. The Active-HDL Lattice Designer Edition Lite supports mixed VHDL and Verilog simulation for Lattice’s FPGA devices, including the 90nm Extreme Performance LatticeSC family as well as the ...