Systems applications such as telecommunications and data communications that employ fault tolerant power delivery architectures usually require "live (or hot) swap" capability for zero downtime. This article presents design considerations related to 48V distributed power architectures using hot swappable, modular power converters.
Hot swap capability imposes special needs to ensure survival of the component that is subjected to live insertion and extraction. In addition, any significant disturbance of either input or output power rails during live insertion/extraction must be prevented. Any significant, even momentary perturbation of either bus could cause the system to malfunction. Individual contacts within a typical connector do not engage/disengage simultaneously, but rather in an undefined random sequence. It is therefore necessary to take steps to ensure orderly power up/down.
Redundancy
The first requirement for fault tolerance is redundancy, i.e., the existence of at least one extra, or "redundant", converter in the system. This is commonly referred to as an N+M array, where N converters are required to satisfy the power requirements, and M additional modules provide redundancy. All modules in the array must be capable of supplying undisturbed power at shutdown or failure of one module, in spite of the sudden increased load demanded of each. The same is true when an additional module is placed on line, suddenly reducing the current demanded of each module. To satisfy these criteria, it's essential that the individual converters share the load current to minimize the dynamic response or recovery required of each.
Parallel Arrays
Second generation Vicor converters (Figure 1) possess features that simplify a redundant parallel array application. The most significant of these include enable/disable capability, a unique master/slave current share control scheme, and the ability to self arbitrate the leadership role. One converter will always assume command of the entire array. These products also have features such as undervoltage lockout, softstart, output current limiting, and remote sense capability. With the resonant zero-current switched topology, line and load regulation is accomplished by controlling the frequency or rate at which pulses of energy are transferred from the primary to the secondary of the isolation transformer. The pulse width, and therefore the energy per pulse, is constant at any given input voltage. The repetition rate is controlled to satisfy the load current demand, while maintaining output voltage regulation. It follows that identical converters will inherently share the load if the switching frequencies are synchronized. The PR pin on 2nd Generation converter modules is a bidirectional port that serves as a parallel load share bus. This port can transmit or receive the synchronizing pulse signal. The controlling module transmits the sync pulse and all other modules listen.
Primary Control and Sense-Pins
The PC (Primary Control) pin, also a bidirectional port, serves as a module status output; it normally is at 6VDC during operation. In a fault condition, such as over temperature or over voltage at the output, PC switches to the low state (approximately 0V with respect to the negative Vin pin). PC periodically toggles high attempting to restart while the fault condition persists, but will remain high only when the fault condition is corrected.
PC also serves as an Enable/Disable input. The converter shuts down if PC is externally pulled low, and will source approximately 2mA while held in the low state. These characteristics facilitate the use of a transistor switch with uncommitted collector or drain for the Enable/Disable function.
The Sense pins provide accurate voltage regulation across the output power bus at the terminus, usually the location of the system’s load. The terminated Sense lines close the regulation control loop, which adjusts the converter output voltage to compensate for voltage drops in the output power bus. Termination of the Sense pins is imperative to maintain output voltage control. Fault tolerant parallel arrays must employ auctioneering diodes in series with the output of each module to the power bus. The converter output currents are summed at the junction of all diodes on the bus. This ensures the integrity of the bus and system operation with a failure of any type, including output short circuit, in any one module. The diode is reversed biased and simply isolates the converter from the bus if its output voltage drops out. Each module’s sense lines must be terminated beyond the diodes, and preferably beyond the hot swap connector at the common bus. A local resistor between the converter’s Sense and power pins ensures that the converter is unable to operate with the control loop open, even momentarily during insertion or extraction. The optimum resistor value is 24 ohms/Volt, i.e., it depends on the output voltage.
The simplest way to keep a converter disabled during the trauma of live insertion or extraction is with a mechanical switch that can be placed in the Off position prior to insertion, then switched On once the connector contacts are firmly mated. Conversely, the switch can be placed in the Off position prior to extraction. The PC pin, which conveniently lends itself to the Enable/Disable function, can be controlled by the switch. If the hot swappable assembly includes locking tabs to secure it once inserted, the locking tabs may be mechanically linked to a microswitch to enable and disable the converter.
An alternative approach automatically disables the converter during insertion and extraction, thus avoiding the need for manual intervention as with a mechanical switch. This eliminates the possibility of human error, i.e., plugging or unplugging while the switch is in the ON position. The method (Figure 2) uses a connector with staggered contacts. Specifically, this approach employs a single short pin for on/off control that is guaranteed to mate last upon insertion and break first during extraction.
Figure 2.Live Swap Protection
The IAM-48 Modul
The IAM48 module contains a series FET switch for on/off control of the 48V bus to the converter input. The on/off control pin has internal pullup and must be pulled low to turn on the 48V bus to the converter module. This part also contains a shunt switch across the output that is in the ON state when the on/off control pin is high (off) with respect to the negative rail. The shunt switch provides a path to rapidly discharge the holdup capacitors when the 48V bus is turned off. In addition to on/off control, the IAM provides inrush current limiting, and in conjunction with the EMI filter module or FiltMod, it also provides transient overvoltage protection. The IAM and FiltMod are generally recommended for telecom applications to ensure compliance with EMC (Electromagnetic Compatibility) standards. In those applications that require hot swap capability, the IAM, or some alternative form of inrush current limiting is required.
The startup sequence upon insertion is as follows: initially, all connector pins, except the short pin, establish contact in an unavoidably random sequence (see Figure 3). During this time, the converter must not be allowed to start. This is ensured because the short pin has not yet made contact, which commands the IAM (via Q1) to remain in the off state. In addition, Q3 pulls the PC pin low, thus disabling the converter. Eventually, the short pin does establish contact after all other pins are firmly seated. The on/off pin of the IAM is pulled low. The IAM in turn allows the 48V bus to ramp up at a controlled rate charging the bus capacitance, which limits the inrush current to a safe level. The converter is also enabled when the IAM turns on, but will not start until the 48V bus reaches the undervoltage lockout threshold at approximately 34V. The converter will not begin to draw current and ramp up the output, however, for at least an additional 100 milliseconds because of the built-in soft start feature. Finally, the converter output voltage runs up to the point where the auctioneering diode is forward biased, at which point the module delivers its equal share of the load.
Figure 3.Live Swap Timing Diagram
The shut down sequence upon extraction is approximately the reverse of the above. The short pin disengages well in advance of all the other pins, which immediately causes the IAM to turn off the 48V. Simultaneously, the converter is disabled. The shunt switch in the IAM rapidly discharges (<50ms) the bus capacitance, while C2 continues to provide current to hold Q3 on. This ensures that the PC pin is held low, well beyond the point in time where the 48V bus decays to the undervoltage lockout threshold. This, in turn, guarantees that the converter cannot process power conversion pulses during the random disengagement of all other contacts.
