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   CHANNEL-E ELECTRONICS EUROPEDESIGNCORNERSTEP-DOWN CONTROLLER


DESIGNCORNER

Next Generation Step-Down Controller Offers High Current Capability with Fast Transient Response, Tracking & Margining

 

Author: Tony Armstrong

 

Many microprocessors, ASICs and digital signal processors (DSPs) need a core power supply and an input/output (I/O) power supply, which must be sequenced during start-up. Designers have to consider the relative voltage and timing of core and I/O voltage supplies during power-up and –down operations to comply with manufacturers’ specifications. Without proper power supply sequencing, latch-up or excessive current draw may occur that could lead to damage to the microprocessor’s I/O ports or the I/O ports of a supporting device such as memory, programmable logic devices (PLDs), field programmable gate arrays (FPGAs) or data converters. To ensure that the I/O loads are not driven until the core voltage is properly biased, tracking of the core supply voltage and the I/O supply voltage is necessary.

 

The penalty for poor tracking or sequencing is often irreparable damage to devices in the system. FPGAs, PLDs, ASICs, DSPs and microprocessors typically have diodes placed between the core and I/O supplies as a component of ESD protection. If supplies violate the tracking requirements and forward bias the protection diodes, the device may be damaged.

 

Voltage sequencing, tracking, and margining have become popular features in DC-to-DC converter modules; however, these functions are less commonly found in DC/DC controller ICs. That is until now, since Linear Technology has recently introduced a synchronous step-down controller which incorporates all three of these power management functions. This new chip, the LTC3770, is also distinguished by its fast transient response, a phase-locked loop (PLL) that allows synchronization to a system clock, and a highly accurate reference. Capable of operating from a 4-V to 32-V input, the current-mode controller can produce a stepped down output at currents up to about 25A, see figure 1.

Next Generation Controller

The LTC3770’s constant on-time, valley current-mode architecture, combined with a very low minimum on-time (50ns typical), allows the control loop to respond quickly to load steps. The LTC3770 can perform RDS(on) current sensing by sensing the voltage drop across the synchronous power MOSFET. Or for systems requiring more-precise control of output current, a conventional sense resistor can be used in the source of the lower MOSFET. In either case, the current limit is user-programmable.

Figure 1. The LTC3770 steps down a 12V input to a 2.5-V output at 10 A

The controller can operate at very low duty cycles. In the extreme case, an output as low as 0.6 V can be supplied from input voltages as high as 32 V - even under no-load conditions. In the applications where such low output voltages are required, the precision of the chip’s voltage reference becomes significant. The LTC3770 specifies an output voltage accuracy of ±0.5% at room temp and ±0.67% from 0oC to 85oC. Across the device’s full operating temperature range (-40ºC to 85ºC), the total error on output voltage is still only ±1%.

 

The controller’s operating frequency can be selected by a single external resistor. For applications that require stringent constant-frequency operation, a phase lock loop allows the LTC3770 to be synchronized to an external clock, which helps reduce EMI.

LTC3770 - Detail of Operation

In normal operation, the top MOSFET is turned on for a fixed interval determined by a one-shot timer. When the top MOSFET is turned off, the bottom MOSFET is turned on until the current comparator ICMP trips, restarting the one-shot timer and initiating the next cycle, refer to figure 2. Inductor current is determined by sensing the voltage between the SENSE+ (PGND on the SSOP package) and SENSE- (SW on the SSOP) pins using a sense resistor or the bottom MOSFET on-resistance. The voltage on the ITH pin sets the comparator threshold corresponding to inductor valley current. The error amplifier EA adjusts this voltage by comparing the feedback signal VFB from a reference voltage set by the VREFIN pin. If the load current increases, it causes a drop in the feedback voltage relative tot the reference. The ITH voltage then rises until the average inductor current again matches the load current.

Figure 2. Functional Block Diagram of the LTC3770 (QFN Package).

At low load currents, the inductor current can drop to zero and become negative. This is detected by the current reversal comparator IREV which then shuts off M2, resulting in discontinuous operation. Both switches will remain off with the output capacitor supplying the load until the ITH voltage rises above the zero current level (0.75V) to initiate another cycle. Discontinuous mode operation is disabled by comparator F when the PFB pin is brought below 0.6V, forcing continuous synchronous operation.

 

The operating frequency is determined implicitly by the top MOSFET on-time and the duty cycle required to maintain regulation. The one-shot timer generates an on-time that is proportional to the ideal duty cycle, thus holding the frequency approximately constant with changes in VIN. The nominal frequency can be adjusted with an external resistor RON.

 

Overvoltage and undervoltage comparators OV and UV pull the PGOOD output low if the output feedback voltage exits a ±10% window around the regulation point after the internal 25ms power bad mask timer expires. Furthermore, in an overvoltage condition, M1 is turned off and M2 is turned on immediately and held on until the overvoltage condition clears.

 

Foldback current limiting is provided id the output is shorted to ground. As VFB drops, the buffered current threshold voltage ITHB is pulled down and clamped to 0.9V. This reduces the inductor valley current level to one tenth of its maximum value as VFB approaches 0V. Foldback current limiting is disabled at start-up.

On-chip Margining

Margining is a resistor-programmable function with the LTC3770. A resistor placed between the programmable margining input pin and ground sets the margining current. This current multiplied by the resistor between the VREFOUT and VREFIN pins sets, determines the margining voltage offset. In addition, the MSB and LSB logic inputs for the margining function together determine whether the IC is in margin high, margin low, or no margin state. This functional capability is particularly useful for those users who need to stress their systems by varying supply voltage during testing.

On-chip Soft-Start and Tracking

The LTC3770 has the ability to either soft start by itself with a capacitor or track the output of another supply. When the device is configured to soft start by itself, a capacitor is connected to the TRACK/SS pin. The LTC3770 is put in a low quiescent current shutdown state if the RUN pin voltage is below 1.5V. The TRACK/SS pin is actively pulled to ground in the shutdown state. Once the RUN pin voltage is above 1.5V, the LTC3770 is powered up. A soft-start current of 1.4mA then starts to charge the soft-start capacitor CSS. Pin Z1 must be grounded for soft-start operation.

 

When the device is configured to track another supply, the feedback voltage of the other supply is duplicated by a resistor divider and applied to the TRACK/SS pin. In this case, Pin Z1 should be tied to INTVCC to turn off the soft-start current in this mode. Therefore, the voltage ramp rate on this pin is determined by the ramp rate of the other supply output voltage.

CONTENT

Next Generation Controller

LTC3770 - Detail of Operation

On-Chip Margining

On-Chip Softstart and Tracking

INFORMATION/CONTACT

LTC3770 (.pdf)

www.linear.com

THE AUTHOR

Tony Armstrong is Product Marketing Manager Power Products Group at Linear Technology Corporation

tarmstrong(at)linear.com

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