Block diagram (click for enlarged view)

Lattice Semiconductor announced the availability of the LatticeMico32, a 32-bit soft microprocessor optimized for Lattice Field Programmable Gate Arrays (FPGAs). Lattice is releasing the Hardware Description Language (HDL) code of the microprocessor core and various peripheral components generated by the LatticeMico32 System, along with selected tools, in an open source format that provides visibility, flexibility and portability. The heart of the product is the LatticeMico32 System development tool suite, which provides a fast and easy way to implement microprocessor designs from platform definition to software development and debug.

The LatticeMico32 microprocessor uses fewer than 2,000 Look Up Tables (LUTs), which results in a cost of less than $1.00 of FPGA logic in select LatticeECP2 FPGAs in high volume. The Reduced Instruction Set Computer (RISC), Harvard-based architecture uses 32-bits for data path and instructions and supports optional data and instruction caches, as well as user-defined instructions. The LatticeMico32 maintains the high performance required for a breadth of applications, with a maximum clock frequency of over 100 MHz (estimated) for LatticeECP2 FPGAs. To accelerate the development of microprocessor systems, several optional peripheral components may be integrated with the LatticeMico32.

These peripheral components are connected to the microprocessor via a Wishbone bus interface, which is a royalty-free, public domain specification. The System development tools, based on the Eclipse C Development Tools (CDT) environment, seamlessly integrate with the Lattice ispLEVER tool suite (version 6.0 SP1 or higher) to enable designers to build microprocessor systems on Lattice FPGAs. The LatticeMico32 System is comprised of three tools: the Mico System Builder (MSB), the C/C++ Software Project Environment (SPE) and the Debugger. The MSB generates platform descriptions and the associated HDL code for hardware implementation. It also enables designers to choose which peripherals should be attached to the microprocessor and the connectivity between them. The C/C++ SPE calls a GNU-based compiler, assembler and linker and enables the development of code targeted to run on platforms created with the MSB. The Debugger allows the designer to observe and control the execution of the code in both an Instruction Set Simulator (ISS) and in physical hardware. To help users rapidly evaluate their microprocessor designs in hardware, Lattice provides a LatticeMico32 Development Kit that includes Lattice’s award-winning ispLEVER software design tools, the LatticeMico32 System development tool suite and a development board. The board is packed with features that help the designer get maximum value from the hardware evaluation process, including Flash memory for loading programs, optional LCD and keyboard interfaces and a variety of other peripheral interfaces including Ethernet, USB and RS232.

Open Source License

This license allows users to ensure that their proprietary designs remain proprietary and allows the implementation and distribution of hardware without the need for a separate license agreement. Additionally, the GNU-based compiler, assembler, linker and debugger, supplied by Lattice, are released under the standard GNU General Public License (GPL) agreement.

Pricing and Availability

The LatticeMico32 System development tools are available now for the LatticeECP and LatticeEC FPGA families. The tools can be downloaded at no charge from the LatticeMico32 Center. The Development Kit is available now and is priced at $995. The Kit includes both the ispLEVER design tools, regularly priced at $695, and the development board, which as a stand-alone is priced at $595. The Kit also can be downloaded from the LatticeMico32 Center. Lattice expects to release versions of the core optimized for the LatticeECP2, LatticeSC and LatticeXP FPGA families throughout the year.