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David Greenfield, Senior Director of HardCopy ASICs at Altera, is introducing the innovations
Embedded Hard-Copy Blocks for more flexibility (click into the picture for enlarged view)
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Altera announced innovations that will be incorporated into upcoming 28-nm FPGAs. Embedded HardCopy Blocks, a new method for partial reconfiguration and embedded 28-Gbps transceivers will improve the density and I/O performance of next-generation Altera FPGAs and strengthen their position versus ASICs and ASSPs.
The rapid growth of bandwidth-intensive applications such as high-definition (HD) video, cloud computing, online data storage and mobile video has created a challenge for both infrastructure and end-user equipment developers.
Embedded HardCopy Blocks
The Embedded HardCopy Blocks are customizable hard intellectual property (IP) blocks that leverage Altera’s HardCopy ASIC capabilities. They are used to harden standard or logic-intensive functions such as interface protocols, application-specific functions, and proprietary custom IP.
Partial reconfiguration
Partial reconfiguration allows designers to reconfigure part of the FPGA while other sections remain running. This is important in systems where uptime is critical because it allows designers to make updates or adjust functionality without disrupting services. Lowering power and cost, partial reconfiguration also improves effective logic density by removing the necessity to place in the FPGA functions that do not operate simultaneously.
Instead, these functions can be stored in external memory and loaded as needed. This reduces the size of the FPGA by allowing multiple applications on a single FPGA, saving board space and reducing power. To date, partial reconfiguration solutions have been time-intensive tasks that required designers to know all of the intricate FPGA architecture details. Altera is simplifying the partial reconfiguration process by building the capability on top of the proven incremental compile design flow in its Quartus® II design software.
28-Gbps transceivers
Altera has developed 28-Gbps embedded transceivers, which will also be implemented in upcoming 28-nm FPGAs. These high-speed transceivers will enable customers to implement next-generation designs such as 400G systems on a single chip without the need for costly external components.
