Chipidea presented a design for an analog-to-digital (ADC) converter. Built for a 90 nanometer CMOS process, the ADC is designed for 1.2 Volt supplied chips and offers an low power dissipation benchmark of 55 mW. The ADC samples at a rate of 1GHz per second, giving it the performance needed for targeted applications. And, with a core cell area of 0.13mm2, it provides designers of digital ICs with a small silicon footprint for SoC solutions.