Xilinx announced the version 8.1 of its PlanAhead software, a hierarchical design and analysis solution that along with Xilinx ISE software delivers a performance advantage for Xilinx Virtex-4 and Spartan-3 FPGAs. PlanAhead streamlines the step between synthesis and place-and-route to give designers more control and insight into how designs are implemented to achieve their target Fmax with fewer design iterations. The tool allows designers to utilize a hierarchical design methodology to minimize routing congestion, simplify clocking and interconnect complexity, and explore implementation options.
Recent customer benchmarks yielded average Fmax performance improvements of 30 percent relative to competing FPGAs, which translates to an average of two speed-grade performance and cost advantage for customers. Complex, multi-clock, high-utilization designs yielded improvements of 56 percent on average over competing solutions - does Xilinx announce. Partial reconfiguration allows customers to save on device count, size, power and cost by allowing predefined portions of an FPGA to be reconfigured while the remainder of the device continues to operate. The new release simplifies the creation of dynamic modules and allows customers to create multiple floorplans for each of their design implementations. Specifically,
PlanAhead 8.1 enhancements offer additional design rule checking, overlap detection, automatic macro creation for module-to-module IO, and a new place-and-route wizard. PlanAhead also controls and manages these implementations in ISE. These improvements make partial reconfiguration more accessible for a wider range of applications, including automotive control functions and software defined radio, where it is already being rapidly adopted. PlanAhead 8.1 provides greater levels of automation and a more intuitive graphical interface. Users can create multiple floorplans, each with its own set of options or strategies and process them in a prioritized manner across multiple processes. Other productivity enhancements include improvements to the schematic viewer for more efficient and intuitive navigation, design analysis and debug and a graphical representation of design hierarchy for enhanced design exploration.
Pricing and Availability
The PlanAhead 8.1 Design Analysis Tool is available on all major operating systems as an option to Xilinx Integrated Software Environment (ISE) software. Single-user licenses at $5,995 include training. Customers can try PlanAhead by downloading a free 30-day evaluation at the Link below.
