Renesas Technology Europe announced the development of its SiP Top-Down Design Environment to boost efficiency when developing system in package (SiP) products combining multiple chips, such as system on chip (SoC) devices, MCUs, and memories, in a single package. It uses a top-down (predictive) design approach in which key characteristics, such as design quality and heat dispersion, are verified during the initial design stage.

The Design Environment replaces the conventional back annotation (analytical) design methodology, in which these characteristics are analyzed at a late stage of the SiP design process, with a top-down design methodology, in which verification is done in the initial SiP design stage. It includes an electromagnetic field analysis tool that supports large-scale substrates. This means it is not necessary to divide up the area to be analyzed. In addition, simulation condition setting and result determination for circuit simulations are automated.

It is therefore possible to estimate noise at the initial design stage based on the electrical characteristics. Further, package models for evaluation of heat dispersion characteristics have until now been created manually by referring to the substrate layout data. As a result, the development of package models for heat dispersion evaluation has been time consuming with limited accuracy for the resulting models.