Pentek released its GateFlow installed-core product Model 6821-422. Based on the model 6821 with 215 MHz A/D Converter VME with dual Virtex-II Pro FPGAs, it includes a factory-installed wideband digital downconverter (DDC) IP core. This DDC is dual-channel version of Pentek's GateFlow IP Core 422 tailored precisely to the various resources of the board. The result is a preconfigured digital software radio subsystem that accepts a front-panel analog RF input and delivers real or complex digital output samples translated to baseband from any frequency slice of the input signal. Applications particularly well suited for Model 6821-422 include wideband recording and systems, real-time DSP and software radio systems, and data-acquisition applications for wideband communication signals used in telemetry and SATCOM. Radar-pulse and beamforming applications especially benefit from the board's many gate, trigger and multi-channel synchronization modes.

Architecture

An Analog Devices AD9430 A/D converter digitizes the incoming signal at 215 MHz and delivers identical sample streams of two independent 422 DDC cores, one in each of the XC2VP50 FPGAs. Within each core, an input stage allows scaling of the A/D samples by a 16-bit gain term. Even and odd samples are split into two streams that are directed into two DDC engines operating in parallel. A direct digital frequency synthesizer (NCO) core generates the desired center frequency of the band of interest. It delivers two complex local oscillator signals, offset slightly in phase, to two complex digital mixers that perform frequency translation of the input signal to 0 Hz. Dual FIR low-pass filters limit the output bandwidth and a final combining, decimation and formatting stage delivers real or complex output samples as required.

The filters can use one of four independent sets of 18-bit coefficients for each of the six decimation settings. The cores also offer a bypass mode that routes the digital samples straight to the output with a simple software switch. The digital output signals are available on two or four front panel data port (FPDP) connectors using several data-packing modes. In addition, the signals can be delivered as low voltage differential signaling (LVDS) through either the VMEbus P2 connector or a second-slot front-panel mezzanine.

Software Support

The Model 6821-422 is supported by Pentek's C-callable ReadyFlow Board Support Libraries. ReadyFlow provides development tools for startup through application completion, allows programming at high, intermediate and low levels to meet various needs, and includes complete source code for all functions.

Pricing and Availability

The Model 6821-422 module is priced starting at $17,495 USD with 10 weeks ARO. Because the GateFlow cores are factory-installed, there are no licensing fees or project use restrictions.