Lattice Semiconductor announced the availability of a free display interface reference design. It illustrates how to use the pre-engineered I/O components within its low cost LatticeECP2 and new LatticeECP2M FPGA families to implement the “7:1” source synchronous LVDS (Low Voltage Differential Signaling) interfaces commonly found in display applications. Lattice also announced its plans for a series of daughter boards that can be used with the existing LatticeECP2 Advanced Evaluation board to test this reference design for display applications.

There are three key challenges associated with implementing high-speed 7:1 LVDS interfaces within FPGAs. First, a high-speed LVDS buffer is required. Second, high-speed data streams need to be serialized and de-serialized. Third, the skew between data and clock bits must be managed in order to avoid eroding the timing margin. The LatticeECP2/M FPGAs contain integrated LVDS receivers and drivers capable of 840 Mbps performance. Built-in gearbox logic allows a 4X reduction in data rate before the data enters the Look-up Tables (LUTs) at the core of the FPGA. Built-in edge clocks minimize the skew between data and clocks. These pre-engineered components allow 7:1 LVDS interfaces to be easily constructed, without the need for manual placement of LUT logic within the devices. The components also provide more timing margin, which permits a more robust and manufacturable design.

Evaluation Kit

To facilitate testing and evaluation of the LatticeECP2/M devices in display applications, Lattice will make a set of daughter cards available for use with its LatticeECP2 evaluation board. These daughter cards will allow image data from a source device, such as a DVD player or PC, to be passed through other vendors’ devices and ultimately be converted into 7:1 LVDS format before being passed though a cable to the LatticeECP2 board. The LatticeECP2 device receiving the data then performs simple image manipulations and passes the data off the board, again using a 7:1 LVDS format. A final board converts the 7:1 LVDS data into DVI format, which is then passed to a display.

Pricing and Availability

The LVDS display interface reference design is available now for free download from the Lattice website.The display interface daughter cards designed for use with the LatticeECP2 evaluation board will be available for purchase in Q4 2006.