LSI Logic introduces the XFI SerDes core with single-lane operation up to 11.1 Gb/s to allow for forward error correction. The XFI SerDes core enables an SoC device to drive an XFP optical module, resulting in compact, cost-effective designs for 10 Gb/s packet processing – a need driven by the explosion of packet-based traffic in network systems. Common to SONET/SDH and Ethernet, 10 Gb/s is widely regarded as a “convergence rate” for carrying packet data, packet voice, video, storage and traditional time division multiplexing traffic. The parallel data path widths are selectable for 32 or 64 bits for flexible integration, allowing users to trade-off cost versus power consumption. The XFI SerDes includes programmable receive equalization and adjustable transmit output swings. To enable thorough test and channel optimization, the SerDes includes integrated BIST (built-in self test) and an adjustable receiver sample point for BER (bit error rate) margin testing. These features enable significant cost reduction and exemplify the commitment LSI places on Design for Manufacturability (DFM). For the first use of XFI SerDes technology, LSI partnered with Ample Communications to develop the Redhawk 2-port 10GE MAC.