Denali Software announced its BCH Error Correction Code (ECC) technology for NAND Flash memory. The technology, as part of Databahn memory controller IP product, is used by hardware engineers in deploying robust NAND Flash-based systems. The solution addresses key issues associated with Single-Level Cell (SLC) and Multi-Level Cell (MLC) NAND and provides significant advantages for system boot applications. The technology is an layer built on top of a Bose, Ray-Chaudhuri, Hocquenghem (BCH) algorithm.

Databahn Flash controller IP is the optimal solution for developing NAND solutions. The architecture is fully configurable to address a wide range of requirements for silicon area, performance, power and device architectures. The Denali Flash memory controller is developed for use in ASIC and FPGA platforms. The controller provides compiler options that allow for maximum flexibility such as bit widths, chip selects, buffering etc. The controller supports several power down options depending on system and chip-level requirements.