Lattice Semiconductor announced the expansion of its ispClock 5300S family of in-system programmable, zero-delay, single-ended clock buffer devices, with the ispClock5308S (8-output) and the ispClock5304S (4-output) chips. These devices provide lower cost alternatives to the previously announced 12-output ispClock5312S. All three members of the E2CMOS-based device family are pin compatible and offer programmable clock skew, termination and interface standard support.
The ispClock5300S devices support four operating configurations, including Zero-Delay Buffer Mode, Combined Zero-Delay and Non-Zero-Delay Fan-out Mode, Dual Fan-out Buffer Mode and Fan-out Buffer Mode with output dividers. The family allows each pin to be configured for the necessary functions individually, resulting in a simple programmable solution that can be customized to suit the design requirements of each circuit board. The ispClock5300S use three, 5-bit on-chip output counters to generate up to 3 clocking frequencies derived from one reference. Output clock frequencies can range up to 267 MHz.
The Universal Fan-out Buffer has a maximum pin-to-pin skew of 100 ps, regardless of bank and frequency, while the maximum cycle-cycle (peak-peak) output jitter is less than 70ps and the period jitter is less than 12 ps (rms). The output skew of each clock net relative to the reference input can be controlled further in delay increments of 156 ps (lead or lag) to compensate for differences in circuit board clock network trace length. The Universal Fan-out Buffers also support a wide variety of popular single-ended logic standards (LVCMOS, LVTTL, HSTL, SSTL) at a variety of voltage levels on the outputs, while reference inputs support single-ended or differential inputs. The input termination and output impedance of each output can be individually tuned to match each trace impedance, which results in clock nets with high signal integrity.
The ispClock5300S devices can integrate multiple types of clock distribution ICs such as Zero-Delay Buffers, Fan-out Buffers and Translators, so designers can easily select the features needed for each individual output pin in their application. In addition, the reference clock input integrates the necessary termination resistors, simplifying interfaces to popular single-ended as well as differential logic interface standards such as LVCMOS, LVTTL, HSTL, SSTL, LVDS, LVPECL, Differential HSTL and Differential SSTL at a variety of voltage levels.Because the outputs of the ispClock5300S devices can be skewed precisely in 156 ps increments, designers can route clock patterns more conveniently, and can compensate for the clock edge arrival delay by skewing each output at the device. The output skew feature of the ispClock5300S devices enables designers to stagger the clock edge in steps of 156 ps, allowing the clocking edge to be spread without introducing jitter.
PAC-Designer Software
The Lattice PC-based mixed signal software design tool, PAC-Designer Version 4.6, provides support for all ispClock5300S devices. Design configurations can be downloaded via the PC parallel port. This version of the PAC-Designer software can be downloaded for free.
Pricing and Availability
Prices for the ispClock5308S and ispClock5304S start at $2.75 and $2.45 respectively in 10KU+ quantities. All three members of the family, in a pin compatible 48-pin TQFP package, are available immediately in both commercial (0˚C to +70˚C) and industrial (-40˚C to +85˚C) temperature grades. PAC-SystemCLK5312S evaluation kits can be used with all three family members and are available through authorized Lattice distributors or on the Lattice website for $295.
