Lattice Semiconductor has expanded its ispClock 5300S family of in-system programmable, single-ended clock buffer devices with the release of the pin-compatible ispClock5316S (16-output) and the ispClock5320S (20-output) ICs. The E2CMOS-based ispClock5300S device family now offers programmable clock skew, termination and interface standard support in a series of five devices with 4 to 20 outputs.
The ispClock5300S devices support four operating configurations, including Zero-Delay Buffer Mode, Combined Zero-Delay and Non-Zero-Delay Fan-out Mode, Dual Fan-out Buffer Mode and Fan-out Buffer Mode with output dividers. The ispClock5300S family allows each pin to be individually configured. Designers now are able to standardize on the ispClock5300S family for all their clock distribution needs, rather than using disparate clock distribution devices from different vendors. The ispClock5300S devices use three, 5-bit on-chip output counters to generate up to 3 clocking frequencies derived from one reference. Output clock frequencies can range up to 267 MHz. The Universal Fan-out Buffer has a maximum pin-to-pin skew of 100 ps, regardless of bank and frequency, while the maximum cycle-cycle (peak-peak) output jitter is less than 70 ps and the period jitter is less than 12 ps (rms).
The output skew of each clock net relative to the reference input can be controlled further in delay increments of 156 ps (lead or lag) to compensate for differences in circuit board clock network trace length. The Universal Fan-out Buffers also support a wide variety of popular single-ended logic standards (LVCMOS, LVTTL, HSTL, SSTL) at a variety of voltage levels on the outputs, while reference inputs support single-ended or differential inputs. The input termination and output impedance of each output can be individually tuned to match each trace impedance, which results in clock nets with high signal integrity.
The Windows-based mixed-signal software design tool, PAC-Designer Version 4.9, provides support for all ispClock5300S devices. Design configurations can be downloaded via the PC parallel port. This version of the PAC-Designer software can be downloaded for free.
Pricing and Availability
Prices for the ispClock5316S device and ispClock5320S device start at $3.80 and $4.10, respectively, in 10KU+ quantities. Both devices are available immediately in a pin compatible 64-pin TQFP package in both commercial (0oC to +70oC) and industrial (-40oC to +85oC) temperature grades. PAC-SystemCLK5312S evaluation kits can be used with all five family members and are available through authorized Lattice distributors or on the Lattice website for $295.
