Silicon Logic Engineering, a semiconductor design services division of Tundra Semiconductor, announced the development of a licensable Interlaken protocol IP core for use in ASIC or FPGA designs. The Interlaken IP Core is scalable, with early versions providing from 10Gbps to 60+Gbps bandwidth across the interface. Future versions will provide over 120Gbps of bandwidth. This scalability suits Interlaken for multiple generations of future network switches, routers and storage equipment. The scalability is achieved through the combination of the SERDES speed (3.125Gbps to 6.375Gbps) and a variable number of SERDES lanes (1 to 24). Designed and tested to be easily synthesizable into many ASIC and FPGA technologies, SLE’s Interlaken IP Core was built to work with off-the-shelf SERDES from most technology vendors. Using the vendor specific proven SERDES allows SLE customers to integrate the Interlaken IP Core into the customer’s technology of choice. The open Interlaken specification was co-written by Cortina Systems and Cisco Systems to provide a far more scalable chip-to-chip interface protocol than previous protocols. Interlaken combines the advantages of the popular SPI4.2 and XAUI interfaces by building on the channelization and per channel flow control features of SPI4.2, and reducing the number of chip I/O pins by using high speed SERDES technology, similar to XAUI.