Lattice Semiconductor announced FPGA support and performance for HyperTransport technology and three memory interfaces. The LatticeSC and LatticeSCM FPGA families (collectively, the “LatticeSC/M” families) now support HyperTransport technology at rates up to 1600Mbps, QDRII+ rates up to 750Mbps, RLDRAM II rates of 800Mbps and DDR2 interface speeds of 667Mbps. HyperTransport technology and the memory interfaces are implemented using the LatticeSC/M families’ innovative PURESPEED I/O technology. The memory controller IP (intellectual property) is implemented in Lattice’s Masked Array for Cost Optimization (MACO) structured ASIC technology.

The MACO embedded structured ASIC blocks are available on LatticeSCM FPGA devices and deliver pre-engineered, standard-compliant IP functions developed by Lattice to shorten end-system time to market. The enhanced DDR, RLDRAM and QDR memory controllers also are available on the LatticeSC/M family of FPGAs, and are supported by the next generation of design tools, the recently announced ispLEVER version 7.0 software design tool suite. There is no IP fee associated with the use of any pre-engineered, MACO-based IP core.

Lattice also is announcing the availability of the PURESPEED I/O Alignment Reference Design. This reference design demonstrates the power of the LatticeSC/M families’ patented Adaptive Input Logic block that delivers data rates of up to 2 Gigabits per second. This reference design is now available and can be downloaded for free.