Lattice Semiconductor announced release 1.3 of its Lattice Diamond design software. It is now integrated with Lattice’s PAC-Designer 6.1 mixed signal design tools, providing design support for Lattice’s programmable mixed signal Platform Manager devices.
In addition, ther software enhances support for the MachXO2 device family by providing final production SSO models and bit streams for the LCMXO2-1200 and LCMXO2-1200U devices, and by adding support for a wafer-level package for the LCMXO2-2000U that is needed for very high volume, cost sensitive applications.
Support for the MachXO2 Device Family
The Diamond design environment enables users to explore design alternatives as they target cost sensitive, low power, high volume applications. The software now includes updated timing and power analysis device information, as well as final production package, bit stream and SSO analysis data based on the actual silicon characterization for the MachXO2 LCMXO2-1200 and LCMXO2-1200U devices.
The tool now aids users who want to migrate their designs to a lower cost device within the same device family while preserving the current package and board layout. This capability is available for both the MachXO2 device family and the higher performance LatticeECP3 FPGA devices. Users are provided pin migration information in the Package view and Spreadsheet views, such as incompatible pins. This pin migration information can also be exported to the Pin Layout file.
Efficient Design Flow
Diamond software incorporates an intuitive, modern GUI that enables several new concepts that help users explore design alternatives to meet their cost, power and performance goals. Diamond 1.3 extends this approach with several new design flow enhancements. For example, projects can now support complex multi-file testbenches and allow multiple design representations for the same design block (such as one description for synthesis and a different description for simulation).
The simulation wizard can automatically determine which files should be set to simulation and pass the correct options to the simulator. In addition, the synthesis design constraints flow is now more intuitive and allows for multiple files that can be managed similar to the back-end preference files. And, when using the Reveal Analyzer, Lattice Diamond’s on-chip debugger, users can now download large trace data amounts and configure complex trigger setups faster than previously possible.
Design Exploration
Diamond 1.3 provides device resource utilization for each logical level of the design hierarchy following synthesis, and enables users to make early design decisions about how to structure their design so that they can optimize utilization of the overall device. Also, in order to explore design alternatives, users can now select the best run when using parallel processing of the multiple implementations provided by Run Manager.
Users can directly select the active implementation in Run Manager and also control which one of the multi-par runs is used so that the rest of the design flow can be focused on the implementation that provides the best placement and routing run for that design. The new Diamond Programmer fully supports the direct programming features of the ispVM System, a stand-alone device programming manager.
Diamond Programmer improves the ease of use of the most common steps such as setting up the cable, scanning the board, and direct programming of the device. Diamond Programmer is available either fully integrated into the Lattice Diamond environment or as a standalone tool.
Integration with PAC-Designer 6.1 Software
Diamond 1.3 software provides an automated simulation environment not previously available to mixed signal designers, and integrates with PAC-Designer 6.1 software to simplify platform management design.
Whether testing the functionality of critical analog I/O pin functions controlled by the Platform Manager’s internal CPLD, or checking the integration of enhanced digital control functions coded in Verilog or VHDL within the Platform Manager’s FPGA control section, PAC-Designer 6.1 software integrates seamlessly with Lattice Diamond 1.3 design tools to compile the entire design, create the necessary stimulus file and then automatically generate initial timing waveforms within the Aldec Active-HDL Simulator.
Third Party Tool Support
The software incorporates Synopsys’ Synplify Pro advanced FPGA synthesis for Windows and Linux. Aldec’s Active-HDL Lattice Edition II simulator is also included for Windows. In addition to the tool support for Lattice devices provided by the OEM versions of Synplify Pro and Active-HDL, Lattice devices are also available in the full versions of Synopsys Synplify Pro and Aldec Active-HDL. Mentor Graphics ModelSim SE and Precision RTL synthesis also support Lattice devices.
Pricing and Availability
Diamond 1.3 software is available now for download from the Lattice website for both Windows and Linux. Once downloaded and installed, the software can be used with either the Lattice Diamond free license or the Lattice Diamond subscription license. The Lattice Diamond free license can be immediately generated upon request from the Lattice website and provides no cost access to many popular Lattice devices such as the MachXO2 and MachXO device families, the LatticeXP2 FPGA family and the LatticeECP2 FPGA family.
The Lattice Diamond free license enables Synopsys Synplify Pro for Lattice synthesis as well as the Aldec Lattice Edition II mixed language simulator. Purchase of the Lattice Diamond subscription license enables all the features of the free license and adds support for all Lattice FPGAs, including the LatticeECP3 devices.
The Lattice Diamond subscription license price is $895 per year.
