Lattice Semiconductor announced FPGA-based support for the Reduced Latency Dynamic Random Access Memory (RLDRAM) I/II memory devices. The LatticeSC and LatticeSCM FPGA families support RLDRAM I/II rates up to 800Mbps. The memory controller IP is implemented in Lattice’s MACO (Masked Array for Cost Optimization) structured ASIC technology. Integrated into the LatticeSC devices are SERDES blocks supporting 3.8Gbps data rates, PURESPEED parallel I/O providing 2Gbps speed, clock management structures, FPGA logic operating at 500MHz and massive amounts of block RAM. Lattice’s Masked Array for Cost Optimization (MACO) embedded structured ASIC blocks also are available on the LatticeSCM devices, delivering pre-engineered, standard-compliant IP functions such as high-speed Memory Controllers, SPI4.2, Ethernet MACs, and PCI Express control functions. MACO IP functions are embedded into the devices, and there is no distinct IP license fee associated with their use. Lattice’s ispLEVER version 7.1 software design tool suite supports a complete HDL-based design and verification flow for LatticeSCM devices, as well as other Lattice programmable device families.
