Altera and Lauterbach announced multi-processor debug support for Altera’s Nios II soft-core embedded processor.

The Lauterbach multi-processor debug solution enables the display and control of multiple Nios II processors in the FPGA. Each Nios II processor can be logically grouped and synchronized, responding to start, step, and break commands simultaneously. Additionally, cross-breakpoint awareness enables a user to halt the system when a set of processors have all reached their assigned breakpoints.

The solution relies on Lauterbach’s TRACE32-PowerView debugger software to provide a unified, graphical environment for debugging one or more Nios II processors. Meanwhile, Lauterbach’s TRACE32-PowerDebug hardware debug module gives designers a hardware connection to their system, operating over a single JTAG connection to the Altera device. External, time-stamped trace capture is also provided over a high-speed Mictor connector to the Nios II system, providing users 512 Mbytes of capture depth at 300 MHz.

The Lauterbach TRACE32-PowerView and TRACE32-PowerDebug are available immediately from Lauterbach. The Nios II processor is available royalty-free, with a perpetual shipper’s license, from Altera as part of development kits featuring the Cyclone and Stratix series of FPGAs. A downloadable evaluation version of the Nios II processor and development tools (including compiler, debugger, and software libraries) is available from the Altera web site at the link below.