Ansoft announces Turbo Package Analyzer (TPA) v5. This latest version of TPA introduces new automation, design flow and simulation capability needed for the extraction of the electrical characteristics of complex high-performance ball-grid array (BGA) style packaging, including wirebond (WBBGA), flip-chip (FCBGA), chip-scale packages (CSPs) and System in Packages (SiP). TPA v5 increases the capacity of the solver to address larger-sized packaging problems and introduces greater automation for generating and/or modifying 3D package layouts.
TPA v5 introduces a new user interface that includes new 2D editing and 3D viewing capabilities, unlimited undo/redo capability, powerful new editing and automation features, such as geometry validation checking and support for VB scripting. Combined with AnsoftLinks, a tool for simplifying data import and export between EDA and CAD packages, TPA v5 generates resistance, inductance and capacitance (RLC) models directly from popular package design tools. It accepts CAD data and fully characterizes the entire package in three dimensions. Extracted sub-circuits can be exported into Nexxim, the company's high-performance circuit simulation software, or existing SPICE tools (SPICE/IBIS format) for subsequent transient analyses, such as crosstalk, overshoot and TDR. TPA v5 is available for Windows XP Professional, Windows XP x64 Edition, Windows Server 2003.
TPA v5 features include:
AC RLC computation for 3D structures
Automated coupled full-package AC RLC extraction using efficient surface triangulation algorithms
DC resistance computation for 3D structures
Automated net-by-net full-package DC resistance extraction using a volumetric (tetrahedral) mesh
Ability to designate source and sink terminal assignment on any given net
New 2D layout editor and 3D viewer
Create advanced wirebond or flip-chip designs from scratch or modify/correct designs imported from third-party layout tools
System-in-Package (SiP) design with multiple wire bond configurations including Trace-to-trace
Die-to-die and Cascaded
User-defined wirebond profiles expanding shapes from JEDEC 4- and 5-point to include arbitrary polylines
Complex solderball models capture true shape and subsequent electrical performance of solderballs and flip-chip solder-bumps
New layer stack-up editor
New via pad stack editor +VB scripting support
Validation check to verify setup, including detection of self-intersecting polygons; disjoint nets; overlapping (DC-shorted) nets, vias and bond wires; illegal connections between bonding pads and bond wires
