Denali announced availability of its design core for PCIe technology. The PCIe core provides hardware developers with a silicon-proven solution for deploying PCI Express technology. The product is part of Denali’s Databahn line of IP, which also includes configurable memory controller IP for DDR and Flash memory. Denali’s PCIe core has been implemented in production silicon. The core has also been tested with all major chipsets and motherboards.

Databahn PCIe IP is a dual-link, dual-mode core that provides an 8-lane interface at the physical layer (20Gb/s). It can be configured as a single link supporting x1, x2, x4, or x8 operations, or as dual-links independently configured for x1, x2, or x4 operation. In the single link mode, the core may be configured as a PCIe Endpoint (EP) or Root Complex (RC). In the dual-link mode, both links can be configured as EPs, or one link can be configured as an RC, the other as an EP. At the physical layer, the core provides an 8-lane PIPE-compatible interface to SERDES devices, with an 8- or 16-bit data width per lane. At the transaction layer, it provides a 64-bit data interface. Denali’s Databahn PCIe core supports the PCIe 1.1 standard, as well as preliminary PCIe 2.0 specifications. Deliverables include synthesizable register transfer level (RTL) code, scripts for synthesis and static timing analysis, layout guidelines, compliance tests and complete documentation. It is verified using Denali’s industry standard PureSpec verification IP and PureSuite compliance suites. Databahn IP is library independent and covers solutions from 130nm to 45nm technologies.