LSI Logic introduces RapidWorx 4.0 – an design tool fos SOC designs. The RapidWorx Design Kit consists of the clock, I/O, IP and memory manager. Features in the I/O manager help users take full advantage of the RapidChip configurable I/Os and the new memory manager provides flexible and configurable options for RapidChip Platform ASIC designers. For the first time, customers have the option of using a clock manager that supports multi-modes, while gaining enhanced viewing capability and significantly increased clock structure capabilities. When customers launch the IP manager, a comprehensive list of RapidChip-specific intellectual property is made available. IP manager seamlessly assigns the appropriate memory and I/O resources for the design. Using RapidWorx, customers can quickly accomplish placed netlist handoff, allowing an accelerated design cycle.

The design kit contains five main tools: floorplanning of the RapidChip slice, physical mapping of these slices, RTL rule checking with physical RTL analysis, physical synthesis with placement optimization, and netlist handoff rule checking. Each tool is launched within the main RapidWorx cockpit. Cross probing is enabled between tools, allowing users to trace signals through different views in the design.