Lattice Semiconductor announced that its LatticeSCM FPGA family-based SPI4.2 MACO (Masked Array for Cost Optimization) cores have been enhanced by adding link layer buffer management options. The family has offered SPI4.2-based cores and bridge reference designs. The platform provides designers with multiple hardened SPI4.2 cores using Lattice’s MACO structured ASIC technology. MACO technology delivers pre-engineered, standard-compliant IP functions. These new features provide designers with a programmable buffer manager capable of:
Up to 16 separate physical FIFOs per TX/RX direction
Packet over-flow and error drop
Both store & forward as well as cut-through operation
