Sandwork Design announced the release of two products for analyzing the data generated during the post-layout simulation of systems on a chip (SoCs) and integrated circuits (ICs). The new Sandwork tools are of special interest to electronic engineers designing and verifying mixed-signal ICs who have to analyze huge sets of extracted netlists with Spice-level simulation waveform data files from industry-standard circuit simulators. Sandwork's waveform viewing technology, coupled with universal wave format coverage, is ideal for these needs. SX CDS-Link ENS, a new product, is integrated into the Cadence Virtuoso custom design platform for the design and verification of complex mixed-signal SoCs. Designers of these chips need to be able to quickly view extracted simulation results to identify problems in the chip design. For example, crosstalk and ground bounce are hard-to-diagnose problems that often go undetected during the post-layout verification process, since the randomly generated RC net names in the simulation results make it extremely difficult to find the original ideal net that is the source of the problem.
By using SX CDS-Link ENS, designers can cross-probe the simulation waveform to the original ideal schematic, quickly identify any problem nodes, and pinpoint the cause by further examining the corresponding layout area. ChipView, now in production, is a visualization and waveform debugging tool based on post-layout RC extracted DSPF (detailed standard parasitic format) netlists. DSPF netlists contain randomly generated net names, making it difficult to debug the netlist itself and to correlate the simulation results. In the past, designers have had no easy way to read these results.
ChipView gives designers an automated tool for debugging extraction problems. With ChipView, designers can now see a topographical stick diagram that is automatically generated by the tool. While viewing the diagram, designers can easily perform such tasks as identifying floating nets and viewing trace resistance and capacitance to see if there are missing traces, opens or shorts, and so on. Designers can see automatically calculated point-to-point trace resistance, resistance gradients, and total trace capacitances for interconnect debugging. With simulation results, ChipView can further provide waveform cross-probing to the auto layout-like stick diagram. ChipView automatically calculates total trace resistance from any two connected extracted nodes, and automatically summarizes top-grounded and top-coupling capacitances.
