Synopsys has donated a library of advanced SystemVerilog assertion checkers defined in the ARM-Synopsys Verification Methodology Manual (VMM) for SystemVerilog to Accellera, the electronic design automation (EDA) organization focused on EDA standards. Provided as SystemVerilog source code, the checkers included in this library have been used by design and verification engineers for the past few years to add SystemVerilog assertions (SVA) to their designs. The donated library contains 20 unique assertion checkers, entirely complementary to Accellera's current OVL of assertion monitors.