Lattice Semiconductor announced the availability of several ispLeverCORE Intellectual Property (IP) modules that are user configurable via its IPexpress design flow. The IPexpress flow is included as a standard feature in Lattice’s ispLEVER design tool suite and supported functions include DDR, Ethernet, FIR, FFT, PCI and Reed-Solomon encoder and decoder. Lattice intends to make several more IPexpress cores available throughout the year. By configuring IP cores using the IPexpress flow, designers are able to simulate, place and route, generate netlists and run static timing analysis with their own logic and selected core parameters – all in real-time.

The IPexpress flow also supports a hardware evaluation capability that makes it possible to create versions of the IP core that operate in hardware for a limited period of time without requiring the purchase of an IP license. The cores available for download from the Lattice IP server (accessible through the ispLEVER IPexpress GUI window) include DDR Controller, Dynamic Block Reed-Solomon Encoder, Dynamic Block Reed-Solomon Decoder, FFT Compiler, FIR Compiler, PCI, Soft Error Detection and Tri-Speed Ethernet MAC. User Guides for these IP modules can be found on the Lattice website (see the link below). The ispLEVER design software, providing support for all Lattice CPLDs and FPGAs, including IPexpress support, is priced at a low $695 suggested resale for a complete PC-based seat.