Xilinx announced FPGA series implemented on 28-nanometer process that slashes total power consumption and offers capacity of up to 2 million logic cells. Xilinx 7 series extend the Targeted Design Platform strategy introduced with the company’s 40nm Virtex-6 and 45nm Spartan-6 FPGA families. The families enable developers to implement programmable solutions in a range of systems that had previously only been achievable in ASSPs or ASICs, including portable ultrasound equipment consuming less than 2 watts and automobile infotainment systems driven by 12 volts, as well as low-cost LTE baseband and femtocell base stations.

Xilinx placed an intense focus on minimizing total power by adopting a unique HKMG (high-K metal gate) process optimized for low static power consumption Working with its foundry partners, Xilinx helped define the new process to achieve FPGA performance requirements, while lowering static power consumption by 50 percent compared to the alternative 28nm high-performance process. Xilinx then applied innovative architectural enhancements to lower dynamic power consumption both for logic and I/O, while also introducing intelligent clock-gating technology with the release of ISE Design Suite 12.

The result is an FPGA series that provides 50 percent lower total power consumption compared to Virtex-6 and Spartan-6 FPGAs and 30 percent lower than alternative 28nm FPGA device families. All 7 series FPGAs share a unified architecture that enables customers to scale their designs up or down in capability. It is also supported by the proven EasyPath FPGA cost reduction solution that further improves productivity by enabling a guaranteed 35 percent cost reduction with no incremental conversion or engineering investment.

Customers who need the lower power or increased system performance and capacity provided in the new 7 series FPGAs can begin designs in Virtex-6 and Spartan-6 FPGAs with the confidence that they can move their designs when the time is right. This unified architecture is facilitated by Xilinx’s adoption of the AMBA AXI interconnect standard enabling plug-and-play IP usage to help customers improve productivity and development costs.

The devices use the same logic architecture, Block RAM, clocking technology, DSP slices, and SelectIO technology and build on previous generations of devices delivered by Xilinx’s patented Virtex series ASMBL block architecture. This next generation ASMBL architecture provides unprecedented flexibility and scalability that enables customers to most effectively utilize the full range of logic densities.

Virtex-7 Family

Delivering a 2X system performance improvement at 50 percent lower power compared to Virtex-6 devices, the high-end Virtex-7 family sets benchmarks with 1.8X greater signal processing performance, 1.6x greater I/O bandwidth, 2X greater memory bandwidth with 2133 Mbps memory interfacing performance, and delivers the industry’s largest density FPGA with 2 million logic cells, which is 2.5X greater density than any previous or existing FPGA.

EasyPath-7 devices are also available for all Virtex-7 FPGAs for a guaranteed 35% cost reduction without requiring any design conversion. Virtex-7 devices enable 400G bridging and switch fabric wired communication systems that are at the heart of the global wired infrastructure, advance RADAR systems, and high-performance computer systems that require single-chip TeraMACC signal processing capabilities, as well as the logic density, performance, and I/O bandwidth required for next generation test and measurement equipment.

The Virtex-7 family will include “XT” extended capability devices with as many as 80 transceivers supporting individual line rates up to 13.1Gbps and devices that provide up to 1.9Tbps serial bandwidth. Also, these devices offer up to 850 SelectIO pins enabling the industry’s greatest number of parallel banks of 72-bit DDR3 memory interfaces supporting 2133Mbps. Future devices will also feature 28Gbps transceivers.

Kintex-7 Family

The Kintex-7 family delivers Virtex-6 family performance at less than half the price for a 2x price/performance improvement while consuming 50 percent less power. The family includes high-performance 10.3Gbps or lower-cost optimized 6.5Gbps serial connectivity, memory, and logic performance required for applications such as high volume 10G optical wired communication equipment.

It also provides a balance of signal processing performance, power consumption, and cost to support the deployment of Long Term Evolution (LTE) wireless networks, meet the aggressive power and cost requirements required for next generation high definition 3D flat panel displays, and deliver the performance and bandwidth needed for next generation broadcast video-on-demand systems.

Artix-7 Family

Delivering 50 percent lower power and 35 percent lower cost compared to the Spartan-6 family, the Artix-7 family utilizes small form-factor packaging and the unified Virtex-series based architecture to deliver the performance required to address cost-sensitive, high-volume markets previously served by ASSPs, ASICs, and low-cost FPGAs.

This new family meets low power performance requirements of battery-powered portable ultrasound equipment, and addresses small form factor, low power requirements for commercial digital camera lens control, as well as the strict size, weight, power, and cost (SWAPc) requirements for military avionics and communications equipment.

Availability

Early access ISE Design Suite software supporting 7 series FPGAs is now available. Initial devices will be available in Q1 of CY2011.